Pipeline and SAR ADCs for Advanced Nodes

The energy efficiency of ADCs has improved by orders of magnitude over the past two decades. Even though process scaling degrades the analog characteristics of transistors, by exploiting, scaling the energy efficiency of recently reported ADCs is approaching fundamental limits [1]. These improvements have been achieved through innovative circuit ideas and through the evolution of ADC architectures. In particular, the SAR ADC architecture has benefitted tremendously from scaling. SAR ADCs are among the most efficient stand-alone converters and form excellent building blocks for more complex architectures including pipeline and highly interleaved ADCs. This chapter builds on material that first appears in [2–4]. Section 2 presents a stand-alone SAR ADC that achieves outstanding efficiency and also shrinks the area needed for a SAR ADC. This architecture uses a chargeinjection cell-based DAC to avoid problems associated with residual settling in conventional SAR ADCs. Further, reuse of the charge-injection cells allows a very small die area. The small size and efficiency make the charge-injection cell SAR ADC an ideal building block for hybrid and interleaved ADCs. We concentrate on pipeline ADCs for the remainder of the chapter. These combine sub-ADCs of moderate resolution with high-performance amplifiers to construct a high-resolution pipeline. In Sect. 3, we present a simple argument that in a two-stage pipeline the first stage should have higher resolution. However, this high-resolution first stage is difficult to achieve with flash-based sub-ADCs. The SAR-assisted pipeline ADC allows a high-resolution first stage that enables a very efficient two-stage pipeline.